As part of the manufacturing process, a device is tested by applying one or more test patterns (called a test series) to it and noting any unexpected results (errors). In cases where devices fail these tests by generating one or more errors and are not immediately discarded thereafter, these devices are then analyzed in a post-processing environment. That is, the device is put back on a tester and subjected to further testing, usually consisting of stepping through the original pattern sequence one pattern at a time until the error is replicated and then extracting internal status information from the chip for additional post-processing. This time-consuming and expensive process would be repeated until each failed pattern was separately replicated, extracted, and analyzed.
Additionally, devices often include error correction circuitry (ECC) to improve reliability of these devices. Although single-bit error correction is the most common such technique, wherein any one erroneous bit within the contents of a given address can be corrected, multiple-bit correction, wherein two or more erroneous bits within the contents of a given address can be corrected, may also be used. When devices with error correction circuitry are subjected to normal pattern testing, no allowances are made to account for the error correction features. Therefore, if the device fails a single test (i.e., if there is a single erroneous bit within the contents of a given address), the device is marked as failed.
Accordingly, there exists a need for improved failure analysis techniques which do not suffer from one or more of the above-described problems associated with conventional failure analysis.